
---------------------------------------------------------------
--
--  Busmacro Package for Virtex-II
--
--
--  Tobias Becker, Xilinx Research Labs, San Jose
--
--  July 20, 2005
--  
--
---------------------------------------------------------------


library IEEE;
use IEEE.std_logic_1164.all;
package busmacro_xc2vp_pkg is


component busmacro_xc2vp_l2r_async_narrow is
    	port (
    		input0 : in std_logic;
    		input1 : in std_logic;
		input2 : in std_logic;
    		input3 : in std_logic;
		input4 : in std_logic;
    		input5 : in std_logic;
		input6 : in std_logic;
    		input7 : in std_logic;
    		output0 : out std_logic;
    		output1 : out std_logic;
		output2 : out std_logic;
    		output3 : out std_logic;
		output4 : out std_logic;
    		output5 : out std_logic;
		output6 : out std_logic;
    		output7 : out std_logic
    	);
	end component;


component busmacro_xc2vp_r2l_async_narrow is
    	port (
    		input0 : in std_logic;
    		input1 : in std_logic;
		input2 : in std_logic;
    		input3 : in std_logic;
		input4 : in std_logic;
    		input5 : in std_logic;
		input6 : in std_logic;
    		input7 : in std_logic;
    		output0 : out std_logic;
    		output1 : out std_logic;
		output2 : out std_logic;
    		output3 : out std_logic;
		output4 : out std_logic;
    		output5 : out std_logic;
		output6 : out std_logic;
    		output7 : out std_logic
    	);
	end component;

    
component busmacro_xc2vp_l2r_async_wide is
    	port (
    		input0 : in std_logic;
    		input1 : in std_logic;
		input2 : in std_logic;
    		input3 : in std_logic;
		input4 : in std_logic;
    		input5 : in std_logic;
		input6 : in std_logic;
    		input7 : in std_logic;
    		output0 : out std_logic;
    		output1 : out std_logic;
		output2 : out std_logic;
    		output3 : out std_logic;
		output4 : out std_logic;
    		output5 : out std_logic;
		output6 : out std_logic;
    		output7 : out std_logic
    	);
	end component;


component busmacro_xc2vp_r2l_async_wide is
    	port (
    		input0 : in std_logic;
    		input1 : in std_logic;
		input2 : in std_logic;
    		input3 : in std_logic;
		input4 : in std_logic;
    		input5 : in std_logic;
		input6 : in std_logic;
    		input7 : in std_logic;
    		output0 : out std_logic;
    		output1 : out std_logic;
		output2 : out std_logic;
    		output3 : out std_logic;
		output4 : out std_logic;
    		output5 : out std_logic;
		output6 : out std_logic;
    		output7 : out std_logic
    	);
	end component;


component busmacro_xc2vp_l2r_async_enable_narrow is		
    	port (
    		input0 : in std_logic;
    		input1 : in std_logic;
		input2 : in std_logic;
    		input3 : in std_logic;
		input4 : in std_logic;
    		input5 : in std_logic;
		input6 : in std_logic;
    		input7 : in std_logic;
		enable0 : in std_logic;
    		enable1 : in std_logic;
		enable2 : in std_logic;
    		enable3 : in std_logic;
		enable4 : in std_logic;
    		enable5 : in std_logic;
		enable6 : in std_logic;
    		enable7 : in std_logic;
    		output0 : out std_logic;
    		output1 : out std_logic;
		output2 : out std_logic;
    		output3 : out std_logic;
		output4 : out std_logic;
    		output5 : out std_logic;
		output6 : out std_logic;
    		output7 : out std_logic
    	);
	end component;


component busmacro_xc2vp_r2l_async_enable_narrow is
    	port (
    		input0 : in std_logic;
    		input1 : in std_logic;
		input2 : in std_logic;
    		input3 : in std_logic;
		input4 : in std_logic;
    		input5 : in std_logic;
		input6 : in std_logic;
    		input7 : in std_logic;
		enable0 : in std_logic;
    		enable1 : in std_logic;
		enable2 : in std_logic;
    		enable3 : in std_logic;
		enable4 : in std_logic;
    		enable5 : in std_logic;
		enable6 : in std_logic;
    		enable7 : in std_logic;
    		output0 : out std_logic;
    		output1 : out std_logic;
		output2 : out std_logic;
    		output3 : out std_logic;
		output4 : out std_logic;
    		output5 : out std_logic;
		output6 : out std_logic;
    		output7 : out std_logic
    	);
	end component;

    
component busmacro_xc2vp_l2r_async_enable_wide is
    	port (
    		input0 : in std_logic;
    		input1 : in std_logic;
		input2 : in std_logic;
    		input3 : in std_logic;
		input4 : in std_logic;
    		input5 : in std_logic;
		input6 : in std_logic;
    		input7 : in std_logic;
		enable0 : in std_logic;
    		enable1 : in std_logic;
		enable2 : in std_logic;
    		enable3 : in std_logic;
		enable4 : in std_logic;
    		enable5 : in std_logic;
		enable6 : in std_logic;
    		enable7 : in std_logic;
    		output0 : out std_logic;
    		output1 : out std_logic;
		output2 : out std_logic;
    		output3 : out std_logic;
		output4 : out std_logic;
    		output5 : out std_logic;
		output6 : out std_logic;
    		output7 : out std_logic
    	);
	end component;


component busmacro_xc2vp_r2l_async_enable_wide is
    	port (
    		input0 : in std_logic;
    		input1 : in std_logic;
		input2 : in std_logic;
    		input3 : in std_logic;
		input4 : in std_logic;
    		input5 : in std_logic;
		input6 : in std_logic;
    		input7 : in std_logic;
		enable0 : in std_logic;
    		enable1 : in std_logic;
		enable2 : in std_logic;
    		enable3 : in std_logic;
		enable4 : in std_logic;
    		enable5 : in std_logic;
		enable6 : in std_logic;
    		enable7 : in std_logic;
    		output0 : out std_logic;
    		output1 : out std_logic;
		output2 : out std_logic;
    		output3 : out std_logic;
		output4 : out std_logic;
    		output5 : out std_logic;
		output6 : out std_logic;
    		output7 : out std_logic
    	);
	end component;


component busmacro_xc2vp_l2r_sync_narrow is
    	port (
    		input0 : in std_logic;
    		input1 : in std_logic;
		input2 : in std_logic;
    		input3 : in std_logic;
		input4 : in std_logic;
    		input5 : in std_logic;
		input6 : in std_logic;
    		input7 : in std_logic;
		ce0 : in std_logic;
    		ce1 : in std_logic;
		ce2 : in std_logic;
    		ce3 : in std_logic;
		clk0 : in std_logic;
    		clk1 : in std_logic;
		clk2 : in std_logic;
    		clk3 : in std_logic;
    		output0 : out std_logic;
    		output1 : out std_logic;
		output2 : out std_logic;
    		output3 : out std_logic;
		output4 : out std_logic;
    		output5 : out std_logic;
		output6 : out std_logic;
    		output7 : out std_logic
    	);
	end component;


component busmacro_xc2vp_r2l_sync_narrow is
    	port (
    		input0 : in std_logic;
    		input1 : in std_logic;
		input2 : in std_logic;
    		input3 : in std_logic;
		input4 : in std_logic;
    		input5 : in std_logic;
		input6 : in std_logic;
    		input7 : in std_logic;
		ce0 : in std_logic;
    		ce1 : in std_logic;
		ce2 : in std_logic;
    		ce3 : in std_logic;
		clk0 : in std_logic;
    		clk1 : in std_logic;
		clk2 : in std_logic;
    		clk3 : in std_logic;
    		output0 : out std_logic;
    		output1 : out std_logic;
		output2 : out std_logic;
    		output3 : out std_logic;
		output4 : out std_logic;
    		output5 : out std_logic;
		output6 : out std_logic;
    		output7 : out std_logic
    	);
	end component;

    
component busmacro_xc2vp_l2r_sync_wide is
    	port (
    		input0 : in std_logic;
    		input1 : in std_logic;
		input2 : in std_logic;
    		input3 : in std_logic;
		input4 : in std_logic;
    		input5 : in std_logic;
		input6 : in std_logic;
    		input7 : in std_logic;
		ce0 : in std_logic;
    		ce1 : in std_logic;
		ce2 : in std_logic;
    		ce3 : in std_logic;
		clk0 : in std_logic;
    		clk1 : in std_logic;
		clk2 : in std_logic;
    		clk3 : in std_logic;
    		output0 : out std_logic;
    		output1 : out std_logic;
		output2 : out std_logic;
    		output3 : out std_logic;
		output4 : out std_logic;
    		output5 : out std_logic;
		output6 : out std_logic;
    		output7 : out std_logic
    	);
	end component;


component busmacro_xc2vp_r2l_sync_wide is
    	port (
    		input0 : in std_logic;
    		input1 : in std_logic;
		input2 : in std_logic;
    		input3 : in std_logic;
		input4 : in std_logic;
    		input5 : in std_logic;
		input6 : in std_logic;
    		input7 : in std_logic;
		ce0 : in std_logic;
    		ce1 : in std_logic;
		ce2 : in std_logic;
    		ce3 : in std_logic;
		clk0 : in std_logic;
    		clk1 : in std_logic;
		clk2 : in std_logic;
    		clk3 : in std_logic;
    		output0 : out std_logic;
    		output1 : out std_logic;
		output2 : out std_logic;
    		output3 : out std_logic;
		output4 : out std_logic;
    		output5 : out std_logic;
		output6 : out std_logic;
    		output7 : out std_logic
    	);
	end component;


component busmacro_xc2vp_l2r_sync_enable_narrow is		
    	port (
    		input0 : in std_logic;
    		input1 : in std_logic;
		input2 : in std_logic;
    		input3 : in std_logic;
		input4 : in std_logic;
    		input5 : in std_logic;
		input6 : in std_logic;
    		input7 : in std_logic;
		enable0 : in std_logic;
    		enable1 : in std_logic;
		enable2 : in std_logic;
    		enable3 : in std_logic;
		enable4 : in std_logic;
    		enable5 : in std_logic;
		enable6 : in std_logic;
    		enable7 : in std_logic;
		ce0 : in std_logic;
    		ce1 : in std_logic;
		ce2 : in std_logic;
    		ce3 : in std_logic;
		clk0 : in std_logic;
    		clk1 : in std_logic;
		clk2 : in std_logic;
    		clk3 : in std_logic;
    		output0 : out std_logic;
    		output1 : out std_logic;
		output2 : out std_logic;
    		output3 : out std_logic;
		output4 : out std_logic;
    		output5 : out std_logic;
		output6 : out std_logic;
    		output7 : out std_logic
    	);
	end component;


component busmacro_xc2vp_r2l_sync_enable_narrow is
    	port (
    		input0 : in std_logic;
    		input1 : in std_logic;
		input2 : in std_logic;
    		input3 : in std_logic;
		input4 : in std_logic;
    		input5 : in std_logic;
		input6 : in std_logic;
    		input7 : in std_logic;
		enable0 : in std_logic;
    		enable1 : in std_logic;
		enable2 : in std_logic;
    		enable3 : in std_logic;
		enable4 : in std_logic;
    		enable5 : in std_logic;
		enable6 : in std_logic;
    		enable7 : in std_logic;
		ce0 : in std_logic;
    		ce1 : in std_logic;
		ce2 : in std_logic;
    		ce3 : in std_logic;
		clk0 : in std_logic;
    		clk1 : in std_logic;
		clk2 : in std_logic;
    		clk3 : in std_logic;
    		output0 : out std_logic;
    		output1 : out std_logic;
		output2 : out std_logic;
    		output3 : out std_logic;
		output4 : out std_logic;
    		output5 : out std_logic;
		output6 : out std_logic;
    		output7 : out std_logic
    	);
	end component;

    
component busmacro_xc2vp_l2r_sync_enable_wide is
    	port (
    		input0 : in std_logic;
    		input1 : in std_logic;
		input2 : in std_logic;
    		input3 : in std_logic;
		input4 : in std_logic;
    		input5 : in std_logic;
		input6 : in std_logic;
    		input7 : in std_logic;
		enable0 : in std_logic;
    		enable1 : in std_logic;
		enable2 : in std_logic;
    		enable3 : in std_logic;
		enable4 : in std_logic;
    		enable5 : in std_logic;
		enable6 : in std_logic;
    		enable7 : in std_logic;
		ce0 : in std_logic;
    		ce1 : in std_logic;
		ce2 : in std_logic;
    		ce3 : in std_logic;
		clk0 : in std_logic;
    		clk1 : in std_logic;
		clk2 : in std_logic;
    		clk3 : in std_logic;
    		output0 : out std_logic;
    		output1 : out std_logic;
		output2 : out std_logic;
    		output3 : out std_logic;
		output4 : out std_logic;
    		output5 : out std_logic;
		output6 : out std_logic;
    		output7 : out std_logic
    	);
	end component;


component busmacro_xc2vp_r2l_sync_enable_wide is
    	port (
    		input0 : in std_logic;
    		input1 : in std_logic;
		input2 : in std_logic;
    		input3 : in std_logic;
		input4 : in std_logic;
    		input5 : in std_logic;
		input6 : in std_logic;
    		input7 : in std_logic;
		enable0 : in std_logic;
    		enable1 : in std_logic;
		enable2 : in std_logic;
    		enable3 : in std_logic;
		enable4 : in std_logic;
    		enable5 : in std_logic;
		enable6 : in std_logic;
    		enable7 : in std_logic;
		ce0 : in std_logic;
    		ce1 : in std_logic;
		ce2 : in std_logic;
    		ce3 : in std_logic;
		clk0 : in std_logic;
    		clk1 : in std_logic;
		clk2 : in std_logic;
    		clk3 : in std_logic;
    		output0 : out std_logic;
    		output1 : out std_logic;
		output2 : out std_logic;
    		output3 : out std_logic;
		output4 : out std_logic;
    		output5 : out std_logic;
		output6 : out std_logic;
    		output7 : out std_logic
    	);
	end component;


end busmacro_xc2vp_pkg;



